1. Field of the Invention
The present invention relates to a method of screening a semiconductor device and, particularly, to a method of screening a semiconductor device by applying a stress voltage.
2. Description of the Related Art
The screening of an initial defect due to the gate oxide film or the p-n junction formed in the semiconductor layer has been performed for the semiconductor chip and the packaged semiconductor device after the wafer process completion. In the screening of a semiconductor chip, a stress voltage is applied to the bonding pad formed on the semiconductor chip by contacting a terminal contacting needle. For the packaged semiconductor device, a stress voltage is applied to the external lead terminal via a socket. Upon application of a stress voltage, a precision equipment, such as an LSI tester or burn-in equipment, is used.
The application of a stress voltage reveals a latent defect so that the semiconductor device with an initial defect is removed, thus reducing the initial malfunction rate after shipping.
Japanese Patent Application Kokai No. 6-29301 has proposed a method of shortening the burn-in time of a packaged semiconductor device by applying a stress voltage before conducting the functional test of a completed semiconductor chip for checking if there is an error in the data outputted from the operation of logic and memory patterns.
In the above voltage application method, however, it is necessary to make a stress application by the operation of a circuit function because a stress voltage is applied to all the elements of a semiconductor device for screening the semiconductor chip and package. Especially when a complicated circuit structure is included in the semiconductor chip and package, a prolonged screening is necessary for applying a stress voltage to all the regions of a semiconductor device due to the circuit operation timing shift. Also, it is necessary to bring the terminal contact needle into contact with the bonding pad of a semiconductor chip with high precision for the voltage application. Similarly, a stress voltage is applied to the outer lead terminal of the semiconductor package via a socket. This requires an expensive facility for the prolonged use of an LSI tester or burn-in equipment.
Thus, there has been a demand for an economical method of screening a semiconductor device that shortens the stress voltage application time for making a latent defect visible.